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Espressif Systems /ESP32-P4 /RMT /INT_RAW

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Interpret as INT_RAW

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0_TX_END_INT_RAW)CH0_TX_END_INT_RAW 0 (CH1_TX_END_INT_RAW)CH1_TX_END_INT_RAW 0 (CH2_TX_END_INT_RAW)CH2_TX_END_INT_RAW 0 (CH3_TX_END_INT_RAW)CH3_TX_END_INT_RAW 0 (TX_CH0_ERR_INT_RAW)TX_CH0_ERR_INT_RAW 0 (TX_CH1_ERR_INT_RAW)TX_CH1_ERR_INT_RAW 0 (TX_CH2_ERR_INT_RAW)TX_CH2_ERR_INT_RAW 0 (TX_CH3_ERR_INT_RAW)TX_CH3_ERR_INT_RAW 0 (CH0_TX_THR_EVENT_INT_RAW)CH0_TX_THR_EVENT_INT_RAW 0 (CH1_TX_THR_EVENT_INT_RAW)CH1_TX_THR_EVENT_INT_RAW 0 (CH2_TX_THR_EVENT_INT_RAW)CH2_TX_THR_EVENT_INT_RAW 0 (CH3_TX_THR_EVENT_INT_RAW)CH3_TX_THR_EVENT_INT_RAW 0 (CH0_TX_LOOP_INT_RAW)CH0_TX_LOOP_INT_RAW 0 (CH1_TX_LOOP_INT_RAW)CH1_TX_LOOP_INT_RAW 0 (CH2_TX_LOOP_INT_RAW)CH2_TX_LOOP_INT_RAW 0 (CH3_TX_LOOP_INT_RAW)CH3_TX_LOOP_INT_RAW 0 (CH4_RX_END_INT_RAW)CH4_RX_END_INT_RAW 0 (CH5_RX_END_INT_RAW)CH5_RX_END_INT_RAW 0 (CH6_RX_END_INT_RAW)CH6_RX_END_INT_RAW 0 (CH7_RX_END_INT_RAW)CH7_RX_END_INT_RAW 0 (RX_CH4_ERR_INT_RAW)RX_CH4_ERR_INT_RAW 0 (RX_CH5_ERR_INT_RAW)RX_CH5_ERR_INT_RAW 0 (RX_CH6_ERR_INT_RAW)RX_CH6_ERR_INT_RAW 0 (RX_CH7_ERR_INT_RAW)RX_CH7_ERR_INT_RAW 0 (CH4_RX_THR_EVENT_INT_RAW)CH4_RX_THR_EVENT_INT_RAW 0 (CH5_RX_THR_EVENT_INT_RAW)CH5_RX_THR_EVENT_INT_RAW 0 (CH6_RX_THR_EVENT_INT_RAW)CH6_RX_THR_EVENT_INT_RAW 0 (CH7_RX_THR_EVENT_INT_RAW)CH7_RX_THR_EVENT_INT_RAW 0 (TX_CH3_DMA_ACCESS_FAIL_INT_RAW)TX_CH3_DMA_ACCESS_FAIL_INT_RAW 0 (RX_CH7_DMA_ACCESS_FAIL_INT_RAW)RX_CH7_DMA_ACCESS_FAIL_INT_RAW

Description

Raw interrupt status

Fields

CH0_TX_END_INT_RAW

The interrupt raw bit for CHANNEL0. Triggered when transmission done.
CH1_TX_END_INT_RAW

The interrupt raw bit for CHANNEL1. Triggered when transmission done.
CH2_TX_END_INT_RAW

The interrupt raw bit for CHANNEL2. Triggered when transmission done.
CH3_TX_END_INT_RAW

The interrupt raw bit for CHANNEL3. Triggered when transmission done.
TX_CH0_ERR_INT_RAW

The interrupt raw bit for CHANNEL0. Triggered when error occurs.
TX_CH1_ERR_INT_RAW

The interrupt raw bit for CHANNEL1. Triggered when error occurs.
TX_CH2_ERR_INT_RAW

The interrupt raw bit for CHANNEL2. Triggered when error occurs.
TX_CH3_ERR_INT_RAW

The interrupt raw bit for CHANNEL3. Triggered when error occurs.
CH0_TX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value.
CH1_TX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value.
CH2_TX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value.
CH3_TX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value.
CH0_TX_LOOP_INT_RAW

The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value.
CH1_TX_LOOP_INT_RAW

The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value.
CH2_TX_LOOP_INT_RAW

The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value.
CH3_TX_LOOP_INT_RAW

The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value.
CH4_RX_END_INT_RAW

The interrupt raw bit for CHANNEL4. Triggered when reception done.
CH5_RX_END_INT_RAW

The interrupt raw bit for CHANNEL5. Triggered when reception done.
CH6_RX_END_INT_RAW

The interrupt raw bit for CHANNEL6. Triggered when reception done.
CH7_RX_END_INT_RAW

The interrupt raw bit for CHANNEL7. Triggered when reception done.
RX_CH4_ERR_INT_RAW

The interrupt raw bit for CHANNEL4. Triggered when error occurs.
RX_CH5_ERR_INT_RAW

The interrupt raw bit for CHANNEL5. Triggered when error occurs.
RX_CH6_ERR_INT_RAW

The interrupt raw bit for CHANNEL6. Triggered when error occurs.
RX_CH7_ERR_INT_RAW

The interrupt raw bit for CHANNEL7. Triggered when error occurs.
CH4_RX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value.
CH5_RX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value.
CH6_RX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value.
CH7_RX_THR_EVENT_INT_RAW

The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value.
TX_CH3_DMA_ACCESS_FAIL_INT_RAW

The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails.
RX_CH7_DMA_ACCESS_FAIL_INT_RAW

The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data